UVM_reg Bit bash sequence for Reserved Field Bits
I am trying to verify 8 bit RW registers and in some of the registers 4 bits are RESERVED lets say [3:0] . My bit bash sequence tries to write in these constant bit and flags me a mismatch error in...
View Article"crave2uvm.h" File Location?
Hello, I have installed CRAVE from github, and I have uvm-systemc 1.0 beta3 as well as systemc 2.3.3 on my machine. The UBUS example from Workshop: UVM-SystemC Randomization - Updates From The...
View ArticleUVM-SC Install Error
I want to install UVM-SC but it compile error. Can I use GCC 5.3 to compile UVM-SC lib? OS: Ubuntu20.04 GCC: 5.3 configure log:...
View ArticleCan we use systemc models for formal verification
If I have fairly accurate cmodels, can I use them formal verification ? Please provide relevant pointers. If not then what are the blockers here ?
View ArticleError: (E112) get interface failed: port is not bound: port...
//Question: i am using a inititator BFm to trigger as you can see and i am binding in sc_main but i sm getting error as discribed in the title, any suggestion ? SC_MODULE( initiator_bfm) {...
View ArticleUVM-SystemC compile error: CXXLD libuvm-systemc.la
Hello, I downloaded the latest systemC systemc-2.3.3, compiled and installed it locally. I also ran some of the tests and an example, and it all works fine. This is on RHEL 6.0, using GCC 6.3....
View ArticleUVM SystemC - Help required for running example tests (make check)
Hello, I am new to UVM SystemC setup. I have installed systemc-2.3.2 & uvm-systemc-1.0-beta4 I don't see any errors while installing the above two. In SystemC installation, I tried: 1. configure...
View Articletlm::tlm_analysis_fifo
Is there any known issue with tlm::tlm_analysis_fifo? I get the following usage error: tlm_analysis_fifo.h:43:11: error: 'nb_put' was not declared in this scope, and no declarations were found by...
View ArticleSystemc Verification
Choices of greetings to everyone here. I am trying to install on my system systemc verification, scv-2.0.1, but I am getting error when I tried to build the source. The error is this" One error...
View ArticleRandomizing sequence items in UVM-SC
Hi All, Just wanted to check if the UVM sequence macros (UVM_DO_ON_WITH and UVM_DO_WITH) which support randomizing the sequence object are yet supported by UVM-SC or not? If not, what is the best way...
View ArticleError: (E521) immediate notification is not allowed during update phase or...
I am trying to use UVM-Connect in my testbench , but when the test is run using ./simv I get this error , it looks like some event is triggered during systemc elaboration , Any idea how to fix this ?...
View ArticleTemplated UVM-SC TB generation using Easier-UVM
The DVCon presentation for UVM-SC (Slide 68) mentions using easier_code UVM generator to get complete UVM-SystemC TB backbone similar to SV UVM. From where can we get the source code for this to use?...
View ArticleUVM-SC for HLS
I am planning to use UVM-SC primarily since we are coming up with HLS design methodology for few IPs. HLS design is in System-C and we want to leverage the verification capabilities of UVM in both...
View ArticleFC4SC error: 'coverage_save' is not a member of 'fc4sc::global'
Hello, OS: Red Hat Enterprise Linux Server release 7.9 I am trying to run fir example but keep getting the error: 'coverage_save' is not a member of 'fc4sc::global' (see below), can you please help...
View ArticleFC4SC XML->YAML via report.py Python script with ZeroDivisionError
Hello, OS: Red Hat Enterprise Linux Server release 7.9 The "/fc4sc/examples/fir" came with "coverage_results_gold.yaml" file. I run the "fir" example which generated "coverage_results.yaml" file....
View Articleis uvm_resource_db::set and uvm_resource_db::read_by_name fullly implememted?
I try to use uvm_resource_db::set and uvm_resource_db::read_by_name to pass the VIF, but failed. after debug , I find the cause is that the return of spell_check is hardcoded to FALSE. My question is...
View Articleis it necessary to take case of “delete item” if the item is create by...
A *item = A::type_id::create("item", this); I am curious about the difference from systemverilog? should I delete item by myself, or will uvm systemc lib totally take over it?
View ArticleCRAVE crave_package_deps.tar.gz dependency not found.
Hello Everyone. I am trying to offline build CRAVE on Red Hat 7.9 but keep getting "crave_package_deps.tar.gz" is missing (see below). Can you please help me find "crave_package_deps.tar.gz"? export...
View ArticleError: complete binding failed: port not bound. the port is the seq_item_port...
In my verification environment, there is a driver operating as a slave mode without the need for a seq_item_port, so its seq_item_port is not connect to seq_item_export of the sequencer. However,...
View ArticleBidirectional TLM1 port/export
I am looking for a bidirectional port/export in UVM SystemC implementation. I could find uvm_*_transport_port/uvm_*_transport_export as well as...
View Articleissues related to CRAVE randmoization
Hi Friends, I have known about uvm-sc and crave for a while. Recently we're looking for integrating CRAVE into our testbench and did some experiment. However, we met some issues and I'm not sure it's...
View ArticleIn [uvm-systemc-1.0-beta5] the example code for UBUS does not work at all...
Scott Peimann and I were working with uvm-systemc-1.0-beta5 examples,(UBUS) and observed a possible issue. The code only works if an address is within the slave[0] with slave[0-3] defined. File:...
View ArticleConnections::Out Connections::IN CCS_INIT_S
I need to know where the below systemc programming keywords, macros, or data types are defined: Connections::Out Connections::IN CCS_INIT_S
View ArticleIs it possible to integrate UVM-SystemC and UVM-ML in the same testbench...
Hello, I'm trying to use UVM-SystemC and UVM-ML within the same environment. My goal is to run a UVM-SystemC testbench to simulate the C model (without using VCS) and use UVM-ML for running RTL...
View ArticleSystemC and Verdi
when using Verdi to view systemC code, Verdi does not support tracing the source (driver) of a signal thru the code window. Is there a new version of Verdi that can do this. Or is there any other tool...
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