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"seed_monitor_on()" globally changes handling of severity Error by use of...

My SystemC-Code is using messages of severity "Error" to intentionally throw exceptions. Suddenly I realize that no longer exceptions are thrown. Analyzing this issue, I targeted the function in my...

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How to drive DUT clock and reset signal in UVM-SystemC?

I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals.  I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it...

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UVM-SystemC now available for public review

The SystemC Verification Working Group (VWG) has made available an early UVM-SystemC Language Reference Manual (LRM) accompanied by a Proof-of-Concept (PoC) implementation for public review. The...

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SCV library installation

Hi,   I wanted to install System C, following  the instructions given in the INSTALL(readme). I was successfully able to configure the package step5 in the INSTALL, i believe it went through...

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How do I use asynchronous reset? in the interface in SV?

If a DUT contains asynchronous reset, whether i can include the reset in the separate interface & instantiate in the TOP module of the test_bench?

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configure is missing for uvm-systemc-1.0-beta1

Saw the UVM-SystemC-1.0-beta1 download link, try to install it, but according to the INSTALL file, I can't find "configure" in the package.  How could I install it?

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UVM-SystemC 1.0-beta1 Released

UVM-SystemC 1.0-beta1 has been released for public review. This update contains compatibility updates to SystemC 2.3.2 and newer compiler versions. It also has a HDL path API implementation, update...

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SCV-2.0.1 Limitations of transaction recording / segmentation fault

Hi, I am using transaction recording with the latest version of SCV (version 2.0.1) and currently I am getting a segmentation fault. I have just searched for a list or something similar with known...

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how to run examples under scv-2.0.0

I want to run examples under scv-2.0.0 I prefer to run compile(g++) in command line

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This is not an option: "scv_smart_ptr" ?

I found a bug in my legacy code that I needed to fix. Even though the bug was easily found the fix troubles me due to limitations of SCV. I have a (template) function "randomRangeEval"() which uses an...

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factory type override of sequence item does not work

Hi, following code that comes with the crave example does not override the sequence item type used by the test:...

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Build issues with UVM-SystemC 1.0-beta1

Although the public review is over, I thought it might still be useful to report the issues I had: The configure script was not present, so I needed to generate it first. It did not work with...

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inherited virtual base class 'sc_core::sc_interface' has private destructor...

I am try to compile tlm1/bidir example from uvm-systemc-1.0-beta1 with SystemC 2.3.2 I got error as below and I have no idea what I have done wrong....

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factory->print() sometimes does not print instance override

When I play around with the factory/basic example from uvm-systemc-1.0-beta1,  In the original example code, it prints the instance override information as below: UVM_INFO @ 0 s: reporter [RNTST]...

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SCV-2.0.1 Fails to compile suit with SCV_DISABLE_USING_NAMESPACES

Hello All, SCV-2.0.1 Compiled with gcc-4.8.1 using the option -DSCV_DISABLE_USING_NAMESPACES. Fails to compile suit while using -DSCV_DISABLE_USING_NAMESPACES. Errors comes from STL library headers,...

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CRAVE status/progress/contributions/...?

Hi all, The last few days I've been playing with the CRAVE version bundled in the SystemC-UVM preview (from...

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CRAVE versus SCV

Hi all, I'm trying to decide which randomization framework to use for an upcoming project. The obvious (and only?) choice seems between CRAVE & SVC. Both have their pros and cons, so it's not like...

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agent_configuration_class

I have an agent having 2 layers, containing 3 components each(sequencer, driver, monitor). I need to configure all these components , then how should I do this by using single agent_configuration_class?

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UVM

What is VIP skeleton? can anyone please explain by an example or sample?

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wait() is not allowed inside run_phase

I am trying to implement SC_JOIN any in a uvm component run phase analogous to SystemVerilog UVM, but the wait statements inside the threads are not executing in the run phase. It will work fine if I...

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